In the related art, in a semiconductor memory device such as a DDR3 SDRAM, a zero quotient (ZQ) calibration is performed to correct an output resistance (Ron) and dynamic on-die termination (ODT) and secure signal quality.
The ZQ calibration includes a ZQ calibration long (ZQCL) process having a long processing time that is generally performed at initialization and a ZQ calibration short (ZQCS) process having a short processing time which is periodically performed after initialization.
In both of the ZQ calibration long (ZQCL) and the ZQ calibration short (ZQCS) processes, it is not possible to receive all of the commands during the ZQ calibration period, and it is required to connect all of devices to a data bus (DQ) in a high-impedance state.
Accordingly, in a semiconductor memory device not structurally provided with a state notification terminal (also known as a ready/busy terminal) for providing the internal state (ready/busy) of the semiconductor memory device by a relationship of the number of terminals, then during ZQ calibration, even if the semiconductor memory device is in a ready state, the ready state cannot be recognized and the memory device cannot be utilized.